Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5. Programmers model
All the GIC-600AE registers have names that are constructed of mnemonics that indicate the
logical block that the register belongs to and the register function.
The following information applies to the GIC-600AE registers:
•
The GIC-600AE implements only memory-mapped registers
•
The GIC-600AE has a single base address, except for the GITS_TRANSLATER register. The
base address is not fixed and can be different for each particular system implementation.
•
The offset of each register from the base address is fixed
•
Accesses to reserved or unused address locations might result in a bus error, depending on the
value of GICT_ERR0CTLR.UE.
•
Unless otherwise stated in the accompanying text:
◦ Do not modify reserved register bits
◦ Ignore reserved register bits on reads
◦ A system reset or a Cold reset, resets all register bits to zero
•
The GIC-600AE ACE-Lite subordinate interface can be 64 bits, 128 bits, or 256 bits wide,
depending on the configuration. The Arm
®
Generic Interrupt Controller Architecture
Specification, GIC architecture version 3 and version 4 defines the permitted sizes of access.
The GIC-600AE guarantees single-copy atomicity for doubleword accesses
•
The GIC-600AE supports data only in little-endian format
•
The access types for the GIC-600AE are as follows:
RO Read-only
RW Read and write
WO Write-only, reads return as UNKNOWN
5.1 Register map pages
The GIC-600AE address map has multiple pages. The number of pages and the address aliasing
depends on the GIC configuration.
The following table shows the register map pages.
Table 5-1: Register map pages
Page offset Page Description
0 GICD 5.2 Distributor registers (GICD/GICDA) summary on page 98
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