Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
4.15.6.8 Clearing error records
After reading a GICT_ERR<n>STATUS register, software must clear the valid register bits so that
any new errors are recorded.
During this period, a new error might overwrite the syndrome for the error that was read
previously. If the register is read or written, the previous error is lost.
To prevent this, most bits use a modified version of write-1-to-clear:
•
Writes to the GICT_ERR<n>STATUS.UE (uncorrectable error records) or
GICT_ERR<n>STATUS.CE (correctable error records) bits are ignored if
GICT_ERR<n>STATUS.OF is set and is not being cleared.
•
Writes to other fields in the GICT_ERR<n>STATUS register are ignored if either
GICT_ERR<n>STATUS.UE or GICT_ERR<n>STATUS.CE are set and are not being cleared.
Similarly, GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 cannot be written, except the counter
fields, if the corresponding GICT_ERR<n>STATUS.MV bit is set, and GICT_ERR<n>ADDR cannot
be written if GICT_ERR<n>STATUS.AV is set.
Recommended recovery sequences are described for each error record in 4.15.6.1 Software error
record 0 on page 72 to 4.15.6.7 ITS command and translation error records 13 and beyond on
page 81.
4.15.7 Bus errors
ACE-Lite bus error syndromes such as bad transactions, and corrupted RAM data reads can be
made to report an ACE-Lite external AXI Subordinate Error (SLVERR).
The GICT_ERR0CTLR.UE bit can be used to enable the SLVERR ACE-Lite bus error for the
syndromes shown in the following table.
Table 4-16: Bus error syndromes
Syndrome Description Direction
SYN_ACE_BAD ACE-Lite transactions are either bad or unrecognized Read and write
SYN_GICD_CORRUPTED Data read from SPI RAM is corrupted Read-only
SYN_GICR_CORRUPTED Data read from SGI or PPI RAM is corrupted Read-only
SYN_ITS_OFF Access to ITS attempted when powered down Read and write
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