Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
Record GICT_ERR<n>MISC0.Data
12 = Uncorrectable •
Address, bits[31:x + 3)]
•
RAM, bits[x + 2:x]
•
ITS, bits[x − 1:0]
Where x = log
2
(ITS)
GICT_ERR<n>MISC0 gives information relating to the corrupted ITS, RAM, and RAM address. The
bit location of a correctable error is also given. The ITS RAM encoding is shown in the following
table.
Table 4-14: ITS RAM encoding
RAM Record 11 Record 12
0 None None
1 Device cache Device cache
2 Collection cache Collection cache
3 Event cache Event cache
4 - Reserved
5 - Reserved
6 - Reserved
7 - Event cache, locked
4.15.6.7 ITS command and translation error records 13 and beyond
The ITS command and translation error records 13+ record uncorrectable command and translation
errors from each configured ITS.
The ITS command and translation error records capture software events so that the operation of
software can be tracked. The software command errors that are captured are uncorrectable errors
only, which require software to correct the command to restart.
The GICT_ERR<n>STATUS.IERR field indicates whether an error is either related to the
architecture (0) or implementation defined (1). In both cases, the full 24-bit syndrome is reported in
GICT_ERR<n>MISC0. Extra data is reported in GICT_ERR<n>MISC1.
The data that is captured for each ITS software syndrome is shown in the following table.
Table 4-15: ITS command and translation errors, records 13 and beyond
MAPD commands
Error mnemonic Encoding IERR Stall Mask Description
MAPD_DEVICE_OOR 0x10801 0 1 CEE A MAPD command has tried to map a device with a DeviceID that is outside the
supported range, or that is beyond the memory allocated
MAPD_ITTSIZE_OOR 0x10802 0 1 CEE A command has tried to allocate an ITT table that is larger than the supported
EventID size
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