Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-51: GICP_CNTENCLR0 bit assignments
31 5 4
0
CNTENReserved
Table 5-64: GICP_CNTENCLR0 bit descriptions
Bits Name Description
[31:5] - Reserved, RAZ
[4:0] CNTEN Counter disable. The CNTEN[n] bit is the disable for counter n. This field resets to an unknown value.
Reads return the state of the counter enables.
Writing:
Bit[n] = 1 Disables counter n
Bit[n] = 0 No effect. To enable a counter, use GICP_CNTENSET0.
Counter n is disabled when CNTEN[n] == 0 or GICP_CR.E == 0.
5.9.7 GICP_INTENSET0, Interrupt Contribution Enable Set Register 0
This register contains the set mechanism for the counter interrupt contribution enables. The
GIC-600AE supports five counters, n = 0-4.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
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