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Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
Check signal Signals covered Width Granularity Check enable
aruserchk aruser ceil(AWUserWidth/8) 1-8 arvalid==1
rvalidchk rvalid 1 1 aresetn==1
rreadychk rready 1 1 aresetn==1
ridchk rid ceil(IdWidthR/8) IdWidthR rvalid==1
rdatachk rdata DataWidthR/8 8 rvalid==1
rrespchk rresp 1 2-4 rvalid==1
rlastchk rlast 1 1 rvalid==1
ruserchk ruser ceil(RUserWidth/8) 1-8 rvalid==1
6.8.2 AXI4-Stream interface parity protection
The GIC-600AE supports AXI4-Stream interface parity protection on point-to-point connections
from the GIC-600AE to another FuSa IP or FuSa interconnect. If a parity fault is detected, the
GIC-600AE flags a fault.
If this protection is not needed, software can disable the appropriate AXI4-Stream Safety
Mechanisms by programming the FMU_SMEN register. When using an interconnect that does not
generate AMBA
®
parity, set FUSA_AXIS_INT_BUSPROT_TYPE=0 to indicate parity, tie off all parity bits
to 1, and disable the AXI4-Stream protection for all blocks in the programmers view.
Assumptions of Use for FuSa purposes
We expect that:
The GIC-600AE connects directly to the far-end IP with only wires and repeater buffers
No complex logic gates such as ADBs or crossbar switches exist in the path, because they could
be a source of MBEs
The ADB FuSa parameters FW_CHK_FIFO_DEPTH and RV_CHK_FIFO_DEPTH are set as the Arm
®
CoreLink
GIC-600AE Generic Interrupt Controller Configuration and Integration Manual describes
The far-end IP checks the parity bits that the GIC-600AE generates
The far-end IP generates the incoming parity bits as the following table describes
Table 6-8: AXI4-Stream interface parity
Check
signal
Signals
covered
Width Granularity Check
enable
tclkchk tclk 1 1 -
tresetchk tresetn 1 1 -
tvalidchk tvalid 1 1 -
treadychk tready 1 1 -
tdatachk tdata n 8 tvalid==1
tstrbchk tstrb ceil(n/8) 1-8 tvalid==1
tkeepchk tkeep ceil(n/8) 1-8 tvalid==1
tlastchk tlast 1 1 tvalid==1
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