ARM CoreLink GIC-600AE User Manual

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
Figure 2-3: Monolithic GIC-600AE with interconnect in an example system
PCIe Root
Complex
SMMU
System interconnect
Core cluster Core cluster
SPIs
Programming
and ITS
interfaces
Key:
Free-flowing channel
Cross-chip
interfaces
GIC
components
ITS Distributor
Redistributor
Redistributor
SPI
Collator
Memory
controller
If the GIC supports LPIs, there must be free-flowing access to main memory. This requirement
is irrespective of the interconnect that is used for routing the AXI4-Stream interfaces. For more
information, see the Arm
®
CoreLink
™
GIC-600AE Generic Interrupt Controller Configuration and
Integration Manual.
The GIC-600AE supports cores that implement only the Armv8.0-A architecture, and later versions
such as Armv8.2-A. The cores must also support the GIC CPU interface with the standard GIC
AXI4-Stream protocol interface. The GIC-600AE implements version 3.0 of the Arm
®
Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
Related information
Components and configuration on page 25
2.2 Compliance
The GIC-600AE interfaces are compliant with Arm specifications and protocols.
The GIC-600AE is compliant with:
•
Version 3.0 of the Arm GIC architecture specification. See the Arm
®
Generic Interrupt
Controller Architecture Specification, GIC architecture version 3 and version 4.
•
The AMBA
®
ACE-Lite protocol. See the AMBA
®
AXI and ACE Protocol Specification.
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Non-Confidential
Page 20 of 268

ARM CoreLink GIC-600AE Specifications

General

Brand	ARM
Model	CoreLink GIC-600AE
Category	Controller
Language	English