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Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
6.2.8 Correctable Error enable
By default, the FMU considers all errors to be Uncorrectable Errors (UEs). To allow the FMU
to treat RAM Single Error Correct (SEC) error indications as Correctable Errors (CEs), set the
FMU_ERR<n>CTLR.CE_EN bit.
When FMU_ERR<n>CTLR.CE_EN is set to 1, the RAM SEC errors set the
FMU_ERR<n>STATUS.CE bit.
When a CE is followed by an UE, FMU_ERR<n>STATUS.IERR is updated to reflect the UE
Safety Mechanism ID. See Prioritized FMU_ERR<n>STATUS registers on page 208 for more
information.
6.2.9 Software interaction
This section describes how software interacts with the FMU.
Initialization
The initialization routine can determine that 44 implemented error records exist, by reading
the FMU_ERRIDR register. It can iterate over the FMU_ERR<n>FR registers to understand the
capabilities of each error record.
All Safety Mechanisms are enabled on reset, which might lead to errors being
logged in the error records. If the system does not support or want to check a
particular safety feature, then the software can disable that Safety Mechanism.
To disable a Safety Mechanism, write the corresponding block ID and Safety Mechanism ID to the
FMU_SMEN register.
To analyze the logged errors, read the FMU_ERR<n>STATUS register.
To clear all logged errors, write all ones to the FMU_ERR<n>STATUS registers.
To enable error reporting through either the ERI or FHI, write to FMU_ERR<n>CTLR.UI or
FMU_ERR<n>CTLR.FI, respectively.
Interrupt handler
When an interrupt is received, the interrupt handling software identifies the error record ID by
reading the FMU_ERRGSR register. The asserted bit[M] indicates that error record M is in error. For
additional information about the error, read the FMU_ERR<M>STATUS register.
FMU_ERR<M>STATUS.IERR indicates which Safety Mechanism reported the error.
If more than one error has been reported by this block to this error record,
FMU_ERR<M>STATUS.OF is asserted. In case of overflow, the error record retains the Safety
Mechanism ID of the first error.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 207 of 268

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