ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-41: GICT_ERR10MISC1 bit assignments
31 x+1 x
0
INFOReserved
63
32
Reserved
Table 5-52: GICT_ERR10MISC1 bit descriptions
Bits Name Description
[63:x
+1]
- Reserved, RAZ
[x:0] INFO Value represents either data that is written to the LPI RAM when an uncorrectable error is detected, or
ITS software information for one of 13, or more, error records.
The value x depends on the width of the LPI RAM, which is set during the configuration of GIC-600AE.
5.8.7 GICT_ERRGSR, Error Group Status Register
This register shows the status of the GIC-600AE Armv8.2 RAS architecture-compliant error records
for correctable and uncorrectable RAM ECC errors, ITS command and translation errors, and
uncorrectable software errors.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
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