Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-34: GITS_CFGID bit assignments
0
ITS_NUMBER
31 28 27 24 23 20 19 18 17 16 15 12 11 8 7
LPI_Credit_
Count
Target_Bits
Collection_
Cache_
Index_Bits
Device_
Cache_
Index_Bits
Event_
Cache_
Index_Bits
MSI_64
Low_Latency_SupportCache_ECC
Reserved
Table 5-42: GITS_CFGID bit descriptions
Bits Name Description
[31:28] Event_Cache_Index_Bits Number of bits that are used to index the Event cache
[27:24] Device_Cache_Index_Bits Number of bits that are used to index the Device cache
[23:20] Collection_Cache_Index_Bits Number of bits that are used to index the Collection cache
[19] - Reserved
[18] Cache_ECC Translation caching has ECC protection
[17] Low_Latency_Support Lock translations in cache support
[16] MSI_64 MSI-64 Encapsulator support. The msi_64 configuration parameter sets the
value of this bit.
[15:12] Target_Bits Number of bits supported for targets
[11:8] LPI_Credit_Count Number of LPI credits − 1. The number_int_credit configuration parameter
minus 1, sets the value of this field.
[7:0] ITS_Number Returns the ITS block ID. The its_id[7:0] tie-off signal controls the ID value. Each
ITS block must have a unique ID.
Related information
Miscellaneous signals on page 258
5.6.7 GITS_PIDR2, Peripheral ID2 Register
This register returns byte[2] of the peripheral ID. The GITS_PIDR2 register is part of the set of ITS
peripheral identification registers.
Configurations
This register is available in all configurations that have one or more ITS blocks.
Attributes
Width 32-bit
Functional group See 5.6 ITS control register summary on page 136 for the address offset,
type, and reset value of this register.
Usage constraints
There are no usage constraints.
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