ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.9.5 GICP_CNTENSET0, Counter Enable Set Register 0
These registers contain the counter enables for each event counter. The GIC-600AE supports five
event counters.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-50: GICP_CNTENSET0 bit assignments
31 5 4
0
CNTENReserved
Table 5-63: GICP_CNTENSET0 bit descriptions
Bits Name Description
[31:5] - Reserved, RAZ
[4:0] CNTEN Counter enable. The CNTEN[n] bit is the enable for counter n. This field resets to an unknown value.
Reads return the state of the counter enables.
Writing:
Bit[n] = 1 Sets the enable for counter n.
Bit[n] = 0 No effect. To disable a counter, use GICP_CNTENCLR0.
Counter n is enabled when CNTEN[n] == 1 and GICP_CR.E == 1.
5.9.6 GICP_CNTENCLR0, Counter Enable Clear Register 0
This register contains the counter disables for each event counter. The GIC-600AE supports five
event counters.
Configurations
This register is available in all configurations.
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