Arm
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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description
[4:0] OVS Overflow status. The OVS[n] bit is the overflow set for counter n. This field resets to zero. Reads return
the state of the overflow status bits.
Writing:
Bit[n] = 1 Sets the overflow status for counter n
Bit[n] = 0 No effect. To clear a counter overflow status, use GICP_OVSCLR0.
When the agent controlling the GIC-600AE sets an OVS bit, it is similar to an OVS bit being set because
of a counter overflow. Setting the OVS bit triggers the overflow interrupt if it is enabled.
5.9.11 GICP_CAPR, Counter Shadow Value Capture Register
This register controls the counter shadow value capture mechanism.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-56: GICP_CAPR bit assignments
31 1 0
Reserved
CAPTURE
Table 5-69: GICP_CAPR bit descriptions
Bits Name Description Type
[31:1] - Reserved -
[0] CAPTURE A write of 1 triggers a capture of all values within the PMU into their respective shadow
registers.
A write of 0 has no effect.
See Snapshot on page 68 for information about other snapshot event triggers.
WO
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