ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description
[5:4] UI Error recovery interrupt for uncorrected errors. Depending on the configuration, returns either:
0b00 The GIC-600AE does not provide an error recovery interrupt for uncorrected errors
0b10 The GIC-600AE provides a controllable error recovery interrupt for uncorrected errors
[3:2] DE Deferring of errors support:
0b00 The GIC-600AE does not support the deferring of errors
[1:0] ED Uncorrected error reporting:
0b01 Uncorrected error reporting is always enabled
5.8.2 GICT_ERR<n>CTLR, Error Record Control Register
This register controls how interrupts are handled.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
If GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.
Bit descriptions
Figure 5-37: GICT_ERR<n>CTLR bit assignments
31 16 15 14 9 8 7 5 4 3 2 1
0
UIFIUEReservedReservedRPReserved
ReservedCFI
Reserved
63
32
Table 5-47: GICT_ERR<n>CTLR bit descriptions
Bits Name Description
[63:16] - Reserved, RAZ
[15] RP 0 = An error response to a transaction is reported
[14:9] - Reserved, RAZ
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