ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-60: GICP_PIDR2 bit assignments
ArchRevReserved
31 8 7 4 3
DES_1
02
JEDEC
Table 5-73: GICP_PIDR2 bit descriptions
Bits Name Description
[31:8] - Reserved, RAZ
[7:4] ArchRev Identifies the version of the GIC architecture with which the PMU complies:
0x3 GICv3
[3] JEDEC Indicates that a JEDEC-assigned JEP106 identity code is used
[2:0] DES_1 Bits[6:4] of the JEP106 identity code. Bits[3:0] of the JEP106 identity code are assigned to
GICP_PIDR1[7:4].
5.10 FMU register summary
The GIC-600AE Fault Management Unit (FMU) functions are controlled through registers that are
identified with the prefix FMU.
Unless otherwise stated in the accompanying FMU register descriptions:
•
do not modify Reserved register bits
•
ignore Reserved register bits on reads
Table 5-74: FMU register summary
Offset Name Type Reset Width Description
0x000 + (n × 64) FMU_ERR<n>FR RO 0xA2 64 Error Record Feature Register
0x008 + (n × 64) FMU_ERR<n>CTLR RW 0x1 64 Error Record Control Register
0x010 + (n × 64) FMU_ERR<n>STATUS RW 0x30_0000 64 Error Record Primary Status register
0xE00 FMU_ERRGSR RO 0x0 64 Error Group Status Register
0xEA0 FMU_KEY RW 0x0 32 FMU Key register
0xEA4 FMU_PINGCTLR RW 0x0 32 Ping Control Register
0xEA8 FMU_PINGNOW RW 0x0 32 Ping Now register
0xEB0 FMU_SMEN WO 0x0 32 Safety Mechanism Enable register
0xEB4 FMU_SMINJERR WO 0x0 32 Safety Mechanism Inject Error register
0xEC0 FMU_PINGMASK RW 0x0 64 Ping Mask register
0xF00 FMU_STATUS RO 0x1 32 FMU Status register
0xFC8 FMU_ERRIDR RO 0x2C 32 Error Record ID Register
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