Arm
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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.10 FMU register summary on page 179 for the address offset, type,
and reset value of this register.
Usage constraints
•
Only accessible by Secure accesses.
•
After a write to this register, poll FMU_STATUS.idle to ensure that the effect of the write is
complete.
•
Do not write to FMU_SMEN and enable or disable a Safety Mechanism that corresponds to a
powered-off block. See Power management on page 208.
If a block is powered-off and then powered-on again, the enabled state of the
Safety Mechanism returns to the default reset state.
Bit descriptions
Figure 5-68: FMU_SMEN bit assignments
Table 5-82: FMU_SMEN bit descriptions
Bits Name Description
[31:24] SMID Safety Mechanism identifier.
See Table 6-2: Safety Mechanism IDs on page 199 for Safety Mechanism ID encodings.
[23:16] - Reserved, RAZ
[15:8] BLK Block identifier.
See Table 6-1: Error record block IDs on page 198 for block ID encodings.
[7:1] - Reserved, RAZ
[0] EN Safety Mechanism enable
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