Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.10.10 FMU_PINGMASK, Ping Mask register
This register configures the ping mask.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.10 FMU register summary on page 179 for the address offset, type,
and reset value of this register.
Usage constraints
•
Only accessible by Secure accesses.
•
Do not change FMU_PINGMASK when background ping is enabled, that is, when
FMU_PINGCTLR.enable == 1.
Bit descriptions
Figure 5-70: FMU_PINGMASK bit assignments
31 0
63 32
ping_mask
4344
Reserved ping_mask
Table 5-84: FMU_PINGMASK bit descriptions
Bits Name Description
[63:44] - Reserved, RAZ
[43:0] ping_mask Ping mask. Bit position corresponds to the GIC block ID. See Table 6-1: Error record block IDs on
page 198 for the block ID designations.
To make the FMU skip a specific block while generating background ping messages, write a one to
the corresponding bit.
For unpopulated GIC blocks, corresponding bits have no effect. The same applies to bit[0], because
the FMU does not ping GICD.
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