ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Functional Safety
Port Direction Granularity Description
paccept_chk Output Redundant paccept port
pdeny_chk Output Redundant pdeny port
pstate_chk Input Redundant pstate port
pactive_chk Output Redundant pactive port
See 6.10 P-Channel and Q-Channel protection on page 232 for more information.
6.4.3 AMBA interface FuSa ports
The following interfaces add the parity extended chk signal bits, as specified in the Arm AMBA
®
Parity Extensions.
In the following table, Granularity refers to the hierarchy or the block in which the ports are
relevant.
Table 6-5: AMBA interface FuSa ports
Port Granularity Description
APB4 interface GICD block APB4 interface added for FMU
AXI4-Stream AMBA
®
parity
All blocks
AMBA
®
parity added to all external AXI4-Stream interfaces
ACE-Lite AMBA
®
parity
GICD/ITS
blocks
AMBA
®
parity added to all external ACE-Lite interfaces
CPU interface (AXI4-
Stream)
Per PPI block irit signal bus (PPI to core) and icct signal bus (core to PPI) parity extensions for AXI4-
Stream
Cross-chip (AXI4-Stream) Per CC chip Parity extensions for AXI4-Stream
The APB port has been added for fault detection and control between the FMU block and the
Safety Island in the SoC.
See 6.8 External interface protection on page 221 for more information.
6.5 Clocks and resets
The GIC-600AE clocks and resets are identical to those signals of the GIC-600, except for the
added redundant clock and reset signals.
The following figure shows how the redundant clock and reset signals are used by the FDC logic.
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