ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.5.1 GICR_MISCSTATUSR, Miscellaneous Status Register
Use this register to test the integration of the cpu_active and wake_request input signals. You can
also use the register to debug the CPU interface enables as seen by the GIC-600AE.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.5 Redistributor registers for SGIs and PPIs summary on page 130 for
the address offset, type, and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-26: GICR_MISCSTATUSR bit assignments
31 30 3 2 1
0
Reserved
wake_request
cpu_active
AccessType
4
Reserved
5
EnableGrp0
EnableGrp1NSecure
EnableGrp1Secure
29
Table 5-31: GICR_MISCSTATUSR bit descriptions
Bits Name Description
[31] cpu_active Returns the status of the cpu_active signal for the core corresponding to the Redistributor whose register is
being read:
0 cpu_active input signal is not active
1 cpu_active input signal is active
This bit is undefined when ProcessorSleep or ChildrenAsleep is set for a core, because the core is presumed
to be powered down.
[30] wake_request Returns the status of the wake_request signal:
0 wake_request signal is not active
1 wake_request signal is asserted
[29:5] - Reserved
[4] AccessType Returns the access type:
0 Secure access
1 Non-secure access
[3] - Reserved
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