Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
Group Control
Errors during commands GITS_FCTLR.CEE (Command Error
Enable)
Other errors such as memory system, or memory allocation errors None
See 4.15.6.7 ITS command and translation error records 13 and beyond on page 81 for
information about all the detected syndromes.
ITS commands must be written by software before they are executed.
The ITS Command queue operates a stall mechanism on any error, irrespective of the
GITS_FCTLR.CEE value. To execute commands, software writes to a Command queue in memory
and then updates the GITS_CWRITER.Offset to indicate that there are commands to run. See 4.7
Getting started on page 59 for more information.
•
Normally, the GITS_CREADR.Offset increments until it matches the GITS_CWRITER.Offset,
wrapping as necessary, to indicate that the Command queue has completed.
•
If an error occurs, GITS_CREADR.Stalled is set, which indicates that processing has stopped
and software intervention is required. If GITS_FCTLR.CEE is set, at least one error is
reported in the relevant error record to aid software debug. You can correct the command
that the GITS_CREADR identifies and then resume the Command queue, by writing to
GITS_CWRITER.Retry. If the command is no longer required, you must rewrite it as a SYNC
command before you resume.
To determine when Command queue execution completes, you can either:
•
Poll GITS_CREADR.Offset until it matches GITS_CWRITER.Offset
•
Put an INT command in the queue and waiting for that interrupt to arrive
If you add an INT command, then we recommend that you enable GITS_FCTLR.CEE and that you
configure the fault handling interrupt or error recovery interrupt to be delivered to a core that can
resolve Command queue issues. See 4.15.5 Error recovery and fault handling interrupts on page
70 for more information.
4.10 LPI caching
If LPI support is configured, the GIC-600AE supports a single LPI cache per chip.
The LPI cache is 2-way set associative based on the lowest bits of the LPI INTID, and stores LPI
properties from the LPI Property table. The relevant set is checked for valid properties as each LPI
arrives in the system.
The cache is fully associative for pending LPIs, which means that the LPI system fills almost all lines
in the cache before sending anything to the Pending tables. The GIC-600AE is not optimized for
collating LPIs that have the same INTID. However the system is designed to reorder and sort the
cache over time. In some circumstances, this behavior can cause duplicated interrupts to not be
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