Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Attributes
Width 64-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
If GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.
Ignores writes if GICT_ERR<n>STATUS.AV == 1.
All bits are RAZ/WI when GICT_ERR<n>STATUS.IERR = 0, 12, or 13.
Bit descriptions
Figure 5-39: GICT_ERR<n>ADDR bit assignments
0
PADDR
Reserved
32
31
63 62 4748
PADDR
NS
Table 5-49: GICT_ERR<n>ADDR bit descriptions
Bits Name Description
[63] NS Non-secure attribute:
0 The address is Secure
1 The address is Non-secure
[62:48] - Reserved, RAZ/WI
[47:0] PADDR The error address. The axis_addr_width configuration parameter controls how many bits in this
field are implemented, that is, from bit[0]-bit[axis_addr_width−1].
5.8.5 GICT_ERR<n>MISC0, Error Record Miscellaneous Register 0
This register contains the corrected error counter and information that assists with identifying the
RAM in which the error was detected.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
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