Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Offset Name Type Reset Width Description Architecture
defined?
0xFF8 GICP_CIDR2 RO 0x05 32 Component ID 2 Register No
0xFFC GICP_CIDR3 RO 0xB1 32 Component ID 3 Register No
5.9.1 GICP_EVCNTRn, Event Counter Registers
These registers contain the values of event counter n. The GIC-600AE supports five counters, n =
0-4.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-46: GICP_EVCNTRn bit assignments
31
0
COUNT
Table 5-58: GICP_EVCNTRn bit descriptions
Bits Name Description
[31:0] COUNT Counter value.
If the counter is enabled, the counter value increments when an event matching
GICP_EVTYPERn.EVENT occurs.
5.9.2 GICP_EVTYPERn, Event Type Configuration Registers
These registers configure which events that event counter n counts. The GIC-600AE supports five
counters, n = 0-4.
Configurations
This register is available in all configurations.
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