Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-52: GICP_INTENSET0 bit assignments
31 5 4
0
INTENReserved
Table 5-65: GICP_INTENSET0 bit descriptions
Bits Name Description
[31:5] - Reserved, RAZ
[4:0] INTEN Interrupt enable. The INTEN[n] bit is the interrupt enable for counter n. This field resets to an unknown
value. Reads return the state of the interrupt enables.
Writing:
Bit[n] = 1 Sets the interrupt enable for counter n
Bit[n] = 0 No effect. To disable a counter interrupt enable, use GICP_INTENCLR0.
The interrupt enable for counter n is enabled when INTEN[n] == 1 and GICP_CR.E == 1.
Overflow of counter n sets GICP_OVSSET0.OVS[n] to 1 and that triggers the PMU interrupt if
INTEN[n] == 1.
5.9.8 GICP_INTENCLR0, Interrupt Contribution Enable Clear Register 0
This register contains the clear mechanism for the counter interrupt contribution enables. The
GIC-600AE supports five counters, n = 0-4.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-53: GICP_INTENCLR0 bit assignments
31 5 4
0
INTENReserved
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