ARM CoreLink GIC-600AE - ITS AXI4-Stream Interface

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
ACE-Lite bus can issue I/O coherent transactions, therefore you can place these tables in shared
memory if necessary. Placing the Command queue in shared memory avoids having to flush the
cache before executing ITS commands.
•
When heavily loaded, the ITS creates a necessary dependency between writes
on its subordinate port and reads on its manager port. You must ensure that any
writes that back up to the subordinate port do not prevent the free-flow of both
reads and writes to the memory.
•
In an ACE system, you must ensure that the write channel from any core cache
that could be snooped, is not blocked by accesses to the ITS subordinate port.
If the write channel is blocked, and the snoop is prevented from completing its
task, a potential deadlock can result.
We recommend that if you place the ITS downstream of an ACE interconnect, then you must not
place tables in shareable memory.
The ITS can issue the following transaction types:
•
256-bit aligned read to the Command queue
•
64-bit aligned read and write to the Device table
•
32-bit aligned read and write to the Interrupt Translation Table (ITT)
•
16-bit aligned read and write to the Collection table
•
If the bypass switch is configured, any bypassed transactions from the subordinate port
ITS issued transactions output the DeviceID on the a<x>user_ signals. The DeviceID is used for
information and does not have to be routed anywhere if it is not required. If the bypass switch is
included, ITS issued transactions are identified by a value of 0 on the a<x>id[0] signal.
The ITS issues only one outstanding transaction per ID. This behavior gives a
maximum of one outstanding write and five outstanding reads, excluding any
transactions from the subordinate port. If this port is combined with the Distributor
ACE-Lite manager port, some of these properties are changed. See Figure 3-8:
GIC-600AE top-level structure options on page 47 for more information.
For more information, see the GICv3 and GICv4 Software Overview.
3.3.3 ITS AXI4-Stream interface
The ITS AXI4-Stream interface is a bi-directional interface of either 16-bit or 64-bit width, for
communication between the ITS and the Distributor on the same chip.
We expect that a typical distributed system is 16 bits wide. When a pre-existing wide interconnect
is used, the 64-bit option allows messages to be efficiently packed.
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