Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
Overflow interrupt
Software can enable the overflow interrupt on a per counter basis by setting the relevant
bit of GICP_INTENSET0. For example, bit[0] enables GICP_EVCNTR0 and bit[1] enables
GICP_EVCNTR1. Similarly, software can disable the overflow interrupt enable by corresponding
writes to GICP_INTENCLR0.
When enabled, the interrupt activates at any of these events:
•
A write to a GICP_OVSSET0 for any counter
•
An overflow on any enabled counter
The GICP_OVSSET0 and GICP_OVSCLR0 registers can be used for save and restore operations
and for testing the correct integration of the pmu_int interrupt signal.
The pmu_int signal can be used to trigger external logic, for example, to trigger a read of the
captured data.
Alternatively, by programming a valid SPI ID into the GICP_IRQCR.SPIID field, the pmu_int signal
SPI is delivered internally in accordance with normal SPI programming.
The GICP_IRQCR.SPIID field must be programmed to 0 if internal routing is not required, or if
internal routing is required, to a legally supported SPI ID. If the programmed ID value is less than 32
or out of range, or for multichip configurations, not owned on chip, the register updates to 0 and
no internal delivery occurs.
Snapshot
Each PMU counter GICP_EVCNTRn has a corresponding GICP_SVRn snapshot register. On a
snapshot event, all five counters are copied to their backup registers so that all consistent data is
copied out over a longer period.
The snapshot events are:
•
A handshake on the 4-phase sample_req/sample_ack signal external handshake
•
A write of 1 to the GICP_CAPR.CAPTURE bit
•
An overflow of an enabled counter when GICP_EVTYPERn.OVFCAP is set
There is only one set of snapshot registers, so data is replaced in multiple capture events.
4.15 Reliability, Accessibility, and Serviceability
The GIC-600AE uses a range of RAS features for all RAMs, which include Single Error Correction and
Double Error Detection (SECDED), and Scrub, software and bus error reporting.
The GIC makes all necessary information available to software through Armv8.2 RAS architecture-
compliant register space.
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