ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Table 5-32: GICR_IERRVR bit descriptions
Bits Name Description
[31:16] Indicates whether a PPI is in an error state:
Bit[n] = 0 If read, PPI[n−16] is not in an error state. Writing 0 has no effect.
Bit[n] = 1 If read, PPI[n−16] is in an error state, so the interrupt is not delivered. Writing 1 clears the error on
PPI[n−16].
[15:0]
valid
Indicates whether an SGI is in an error state:
Bit[n] = 0 If read, SGIn is not in an error state. Writing 0 has no effect.
Bit[n] = 1 If read, SGIn is in an error state, so the interrupt is not delivered. Writing 1 clears the error on SGIn.
5.5.3 GICR_SGIDR, SGI Default Register
This register controls the default value of SGI settings, for use in the case of a Double-bit Error
Detect Error (DEDERR).
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.5 Redistributor registers for SGIs and PPIs summary on page 130 for
the address offset, type, and reset value of this register.
Usage constraints
Only accessible by Secure accesses. This register does not support 32-bit writes.
Bit descriptions
Table 5-33: GICR_SGIDR bit descriptions
Bits Name Description
[3] + 4n:
[63, 59, 55, 51, 47, 43, 39, 35, 31, 27, 23, 19, 15, 11, 7, 3]
- Reserved, RES0
[2] + 4n:
[62, 58, 54, 50, 46, 42, 38, 34, 30, 26, 22, 18, 14, 10, 6, 2]
GRPMOD As GICR_IGRPMODR0 register
[1] + 4n:
[61, 57, 53, 49, 45, 41, 37, 33, 29, 25, 21, 17, 13, 9, 5, 1]
GRP As GICR_IGROUPR0 register
[0] + 4n:
[60, 56, 52, 48, 44, 40, 36, 32, 28, 24, 20, 16, 12, 8, 4, 0]
NSACR 1 = Allow Non-secure access to interrupt <n>
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 134 of 268