Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Table 5-48: GICT_ERR<n>STATUS bit descriptions
Bits Name Description
[31] AV Indicates if the address is valid:
0 GICT_ERR<n>ADDR is not valid
1 GICT_ERR<n>ADDR contains an address that is associated with the highest priority error that this record stores.
Only present in record 0.
[30] V Indicates if this register is valid:
0 GICT_ERR<n>STATUS is not valid
1 GICT_ERR<n>STATUS is valid. One or more errors are recorded.
[29] UE Uncorrectable error bit.
SBZ in Correctable Error (CE) records.
[28] ER Indicates that at least one error has been reported over ACE-Lite.
Set for record 0 only, and only for accesses to corrupted data, and bad incoming access.
[27] OF Record has overflowed
[26] MV Indicates if the GICT miscellaneous registers are valid:
0 GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 are not valid
1 GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 are valid
[25:24] CE Correctable error. Indicates errors that are correctable as shown in Table 4-7: Error handling records on page 71:
0b00 No CE recorded
0b10 At least one CE recorded
[23:22] - Reserved, RAZ/WI
[21:20] UET Uncorrectable error type. RES0 unless UE == 1, in which case:
0b10 UEO, uncorrectable error and restartable
0b11 UER, uncorrectable error and recoverable
[19:16] - Reserved, RAZ/WI
[15:8] IERR Implementation-defined error code.
Returns information that Table 5-51: GICT_ERR<n>MISC0.Data field encoding on page 155 shows.
This field is RO apart from record 0 and record 13 (and above).
[7:0] SERR Architecturally defined primary error code.
Returns information that Table 5-51: GICT_ERR<n>MISC0.Data field encoding on page 155 shows. See the Arm
®
Architecture Reference Manual Supplement Reliability, Availability, and Serviceability (RAS), for Armv8-A for more
information about this field.
This field is RO apart from record 0.
5.8.4 GICT_ERR<n>ADDR, Error Record Address Register
This register contains the address and security status of the write. This register is only present for
GICT software record 0.
Configurations
This register is available in all configurations.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 152 of 268
To Next Page
Loading...