ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Signal descriptions
A.8 Interdomain signals
Interdomain signals are routed between domains.
Signal definitions
Table A-9: Interdomain signals
Signal Direction Description
wakeup_sm_*
wakeup_ms_*
*_async_*
Input and output,
depends on signal
name
These signals connect between halves of a CoreLink
™
ADB-400. See the Arm
®
CoreLink
™
ADB-400 AMBA
®
Domain Bridge User Guide.
If you instantiate domain levels, you must ensure that matching input and output
pairs of interdomain signals connect together directly, and are not separated by
synchronizers.
A.9 Interchip AXI4-Stream interface signals
The following table shows the GIC-600AE interchip signals.
Signal definitions
Table A-10: Interchip signals
Distributor to remote chip AXI4-Stream interface, icdr bus
Signal Direction Description
icdrtready Input
icdrtvalid Output
icdrtdata[63:0] Output
icdrtlast Output
AXI4-Stream compliant bus for communication between the Distributor and a remote chip. The
interface is fully credited and can be sent over any free-flowing interconnect.
icdrtwakeup Output Registered wake signal to indicate that a message is arriving or is about to arrive on the icdr bus.
The icdrtvalid and icdrtready signals control data transfer.
icdrtdest[<chip_addr_width>
−1:0]
Output Specifies the destination remote chip. The signal width is set using the chip_addr_width
configuration option.
This signal is only present on the Distributor.
icdrtkeep Output Indicates the data bytes that must be transferred.
This signal is only present on the Distributor.
Remote chip to Distributor AXI4-Stream interface, icrd bus
Signal Direction Description
icrdtready Input
icrdtvalid Output
icrdtdata[63:0] Output
icrdtlast Output
AXI4-Stream compliant bus for communication between the remote chip and the Distributor. The interface is
fully credited and can be sent over any free-flowing interconnect.
icrdtwakeup Output Registered wake signal to indicate that a message is arriving or is about to arrive on the icrd bus. The icrdtvalid
and icrdtready signals control data transfer.
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