ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
For information about the purpose of each PPI used by the processor core in your system, refer to
the processor Technical Reference Manual.
4.1.3 SPIs
A Shared Peripheral Interrupt (SPI) is generated by a peripheral that is accessible across the whole
system such as a USB receiver, and which can connect to several cores. SPIs are typically used for
peripherals that are not tightly coupled to a specific core.
You can program each SPI to target either a particular core or any core. Activating an SPI on one
core activates the SPI for all cores. That is, the GIC-600AE allows at most one core to activate an
SPI. The settings for each SPI are also shared between all cores.
SPIs are generated either by wire inputs or by writes to the ACE-Lite subordinate programming
interface. The GIC-600AE can support up to 960 SPIs, corresponding to the external spi
input signals on the SPI Collator. The number of SPIs available depends on the implemented
configuration. The permitted values are ID32-ID991, in steps of 32. The first SPI has an ID number
of 32.
During configuration of the GIC, you can apportion some or all SPIs to be message-based or you
can set all SPIs to be physical spi signals. If an SPI ID is allocated as a physical spi input signal, then
software can still use that SPI ID as a message-based SPI, provided that the hardware ensures that
the spi signal is held to a logic level that represents the inactive state.
You can configure whether each SPI is triggered on a rising edge or is active-HIGH level-sensitive.
The GIC-600AE provides an option, through a parameter, to include one or both of a synchronizer
or inverter for each SPI interrupt wire.
The GIC-600AE uses the SPI Collator to convert wire-based interrupts into messages to reduce
system wiring, and to allow more aggressive clock gating of the GIC to reduce power consumption.
See 3.5 SPI Collator on page 42 for more information.
SPIs are programmed through the GICD register address space, which is spread coherently across
all configured chips to provide a single view to the Operating System (OS).
You can trigger a valid SPI by using the GICD_SETSPI_NSR or GICD_SETSPI_SR registers, see
the Arm
®
Generic Interrupt Controller Architecture Specification, GIC architecture version 3 and
version 4.
4.1.4 LPIs
Locality-specific Peripheral Interrupts (LPIs) are always message-based, and can be from a peripheral
or from a PCIe root complex.
An LPI targets only one core. LPIs are generated when the peripheral writes to the ITS. The ITS
contains the registers to control the generation and maintenance of LPIs. The ITS provides INTID
translation, allowing peripherals to be owned directly by a virtual machine if an SMMU is also
present for those peripherals.
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