ARM CoreLink GIC-600AE User Manual

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
Figure 3-1: GIC-600AE Distributor
Wake
Request
Power
controller
Cross-chip interface
GIC
Distributor
(GICD)
ACE-Lite subordinate
interface
ACE-Lite manager
interface
Q-Channel
device interface
Q-Channel
ITS power control
SPIs
SPI
Collator
Redistributors ITSs
chip_id
gicp_allow_ns
gict_allow_ns
gicd_page_offset
fault_int
err_int
pmu_int
sample_req
sample_ack
AXI4-Stream
interface
The Distributor is the main hub of the GIC and it implements most of the GICv3 architecture
including:
•
Programming, forwarding, and prioritization of SPIs, see 4.1.3 SPIs on page 49
•
Caching and forwarding of LPIs, see 4.1.4 LPIs on page 49
•
SGI routing and forwarding
•
Register programming of all registers apart from GITS_TRANSLATER
•
Power control of cores and Redistributor blocks
3.1.1 Distributor AXI4-Stream interfaces
The GIC-600AE uses AXI4-Stream interfaces to communicate between blocks.
These interfaces are:
•
fully credited
•
ic<xy>tready. Where xy can be cd, dc, pd, dp, id, di, rd, dr, or dw.
Irrespective of the interconnect that is used, packets must not be reordered between endpoints,
for example, between the Distributor and a single Redistributor block. Packets must never be
interleaved.
For information about AXI4-Stream signals, see the AMBA
®
4 AXI4-Stream Protocol Specification.
The following table lists the AXI4-Stream input interfaces.
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ARM CoreLink GIC-600AE Specifications

General

Brand	ARM
Model	CoreLink GIC-600AE
Category	Controller
Language	English