ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-58: GICP_CR bit assignments
31 1 0
EReserved
Table 5-71: GICP_CR bit descriptions
Bits Name Description
[31:1] - Reserved
[0] E Global counter enable:
0 No events are counted and the values in GICP_EVCNTRn do not change
1 The counters are enabled
Resets to 0.
This bit takes precedence over the GICP_CNTENSET0.CNTEN bits.
5.9.14 GICP_IRQCR, Interrupt Configuration Register
This register controls which SPI is generated when a PMU overflow interrupt occurs.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
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