Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.2.10 GICD_ICERRRn, Interrupt Clear Error Registers
These registers can clear the error status of an SPI or return the error status of an SPI. Each
register monitors 32 SPIs and the GIC-600AE has 30 registers, GICD_ICERRR1-GICD_ICERRR30.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
Usage constraints
The Distributor provides up to 30 registers to support 960 SPIs. If you configure the GIC-600AE
to use fewer than 960 SPIs, it reduces the number of registers accordingly. For locations where
interrupts are not implemented, the register is RAZ/WI.
Bit descriptions
In earlier versions of the GIC-600AE, this register was known as the GICD_IERRRn.
Figure 5-10: GICD_ICERRRn bit assignments
31 0
Status
Table 5-12: GICD_ICERRRn bit descriptions
Bits Name Description
[31:0] Status Indicates whether an SPI is in an error state:
0 If read, the SPI is not in an error state and programming is valid. Writing 0 has no effect.
1 If read, the SPI is in an error state and programming is not valid. Writing 1 clears the error.
The SPI that a bit refers to, depends on its bit position and the base address offset of the GICD_ICERRRn, that is, SPI =
32×n + bit[number].
5.2.11 GICD_CFGID, Configuration ID Register
This register contains information that enables test software to determine if the GIC-600AE system
is compatible.
Configurations
This register is available in all configurations.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 112 of 268
To Next Page
Loading...