Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Attributes
Width 64-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-11: GICD_CFGID bit assignments
31 21 20 15 14 13 12 11 8 7 4 3 1 0
SNUMSPISReserved
63 47 44 43 40 39 36 35 32
AFF0Reserved AFF1AFF2AFF3
Reserved
4852
PEW
53
SO
Reserved
LPIS
DLPI
AFSL
Table 5-13: GICD_CFGID bit assignments
Bits Name Description
[63:53] - Reserved, returns zero
[52:48] PEW Width of lower part of on-chip core number field, ceil[log
2
(max_pe_on_chip)]. max_pe_on_chip is a configuration
option that is set during system integration, which defines the maximum number of cores on a single chip in the system.
See 4.16.7 LPI multichip operation on page 93 for more information.
[47:44] AFF3 Returns the Affinity3 bits
[43:40] AFF2 Returns the Affinity2 bits
[39:36] AFF1 Returns the Affinity1 bits
[35:32] AFF0 Returns the Affinity0 bits
[31:21] - Reserved, returns zero
[20:15] SPIS Number of SPI blocks supported
[14] AFSL Chip affinity selection level
[13] DLPI Direct LPI registers supported
[12] LPIS LPI supported
[11:8] - Reserved, returns zero
[7:4] CNUM Chip number
[3:1] - Reserved, returns zero
[0] SO Socket online status:
0 chip is offline
1 chip is online
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