Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.10.3 FMU_ERR<n>STATUS, Error Record Primary Status register
This register indicates information relating to the recorded errors. Software can write to this
register to clear the error records that FMU_ERRGSR reports.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.10 FMU register summary on page 179 for the address offset,
type, and reset value of this register. This register is only reset by the
dbg_[<domain>]reset_n signal.
Usage constraints
•
Only accessible by Secure accesses.
•
After a write to this register, poll the FMU_STATUS register to ensure that the effect of the
write is complete. Until the write takes effect, that is, FMU_STATUS.idle == 1 then:
◦ The corresponding bit of FMU_ERRGSR might still report as 1.
◦ Any interrupts caused by this record might still be asserted.
◦ Any new error that occurs, is treated as a second error recording on top of this error, and
causes an overflow to be set.
◦ Any read of this register might return the old value, or if a new error has been recorded,
then the newly recorded value.
•
Do not write to an FMU_ERR<n>STATUS that corresponds to a powered-off block. See Power
management on page 208.
Bit descriptions
Figure 5-63: FMU_ERR<n>STATUS bit assignments
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 182 of 268
To Next Page
Loading...