Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Table 5-77: FMU_ERR<n>STATUS bit descriptions
Bits Name Description Type
[63:40] - Reserved, RAZ -
[39:32] BLKID This field is only valid for error record 0 (GICD). Valid only when
FMU_ERR<n>STATUS.V==1 and FMU_ERR<n>STATUS.IERR==19 (FMU ping ACK error).
When there is a PING_ACK timeout error, this field indicates the block ID of the remote GIC
block that caused the error.
If software uses FMU_SMINJERR for error injection, this field is not updated when a
PING_ACK timeout error is reported.
RO
[31] - Reserved, RAZ -
[30] V Indicates if this register is valid:
0 FMU_ERR<n>STATUS is not valid
1 FMU_ERR<n>STATUS is valid. One or more errors are recorded.
Write 1 to clear. When clearing this bit, FMU_ERR<n>STATUS.UE and
FMU_ERR<n>STATUS.CE must also be cleared.
RW
[29] UE Uncorrected error bit.
Write 1 to clear. When clearing this bit, FMU_ERR<n>STATUS.V must also be cleared.
If FMU_ERR<n>STATUS.V is set to 0, this bit is not valid and reads unknown.
RW
[28] - Reserved, RAZ -
[27] OF Record has overflowed.
Write 1 to clear.
RW
[26] - Reserved, RAZ -
[25:24] CE Corrected error bit:
0b00 No errors were corrected
0b10 One or more errors were corrected
Write 0b10 or 0b11 to clear.
If FMU_ERR<n>STATUS.V is set to 0, this field is not valid and reads unknown.
RW
[23:22] - Reserved, RAZ -
[21:20] UET Uncorrected error type.
0b11 Uncorrected error records
This field is not valid and reads unknown if either of the following conditions are true:
•
FMU_ERR<n>STATUS.V is set to 0
•
FMU_ERR<n>STATUS.UE is set to 0
RO
[19:16] - Reserved, RAZ -
[15:8] IERR Implementation-defined error code.
See Table 6-2: Safety Mechanism IDs on page 199 for Safety Mechanism ID encodings.
If FMU_ERR<n>STATUS.V is set to 0, this field is not valid and reads unknown.
RW in error record 0 and
13+, otherwise RES0
[7:0] SERR Architecturally defined primary error code.
Returns information shown in Table 5-51: GICT_ERR<n>MISC0.Data field encoding on page
155.
RO in error record 0,
otherwise RW
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