Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
4. Operation
This chapter provides an operational description of the GIC-600AE.
4.1 Interrupt types
The GIC-600AE manages SPIs, SGIs, PPIs, and LPIs.
4.1.1 SGIs
Software Generated Interrupts (SGIs) are inter-processor interrupts, that is, interrupts generated from
one core and sent to other cores.
Each core in the system processes an SGI independently of the other cores. The priority of an SGI,
and other settings, are also independent for each core.
SGIs are generated by writing to System registers in the CPU interface of the core that generates
the interrupt. SGIs are edge triggered.
Up to 16 SGIs can be recorded for each target core, where each SGI has a different INTID in the
ID0-ID15 range.
4.1.2 PPIs
A Private Peripheral Interrupt (PPI) identifies an interrupt source, such as a timer, that is private to
the core, and which is independent of the same source for another core. PPIs are typically used for
peripherals that are tightly coupled to a particular core.
Interrupts that connect to the PPI inputs associated with one core, are only sent to that core. Each
core processes a PPI independently of other cores. The settings of a PPI are also independent for
each core.
A PPI is unique to one core. However, the PPIs to other cores can have the same INTID. Up to 16
PPIs can be recorded for each target core, where each PPI has a different INTID in the ID16-ID31
range.
PPI signals are active-LOW level-sensitive by default. However, you can set a PPI signal to be either
level-sensitive or edge-triggered using GICR_ICFGR1. See the Arm
®
Generic Interrupt Controller
Architecture Specification, GIC architecture version 3 and version 4 for more information.
The GIC-600AE provides an option, through parameters, to include one or both a synchronizer
and inverter on each PPI interrupt signal. See 3.2.4 Redistributor PPI signals on page 33 for more
information.
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