Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Table 5-55: GICT_DEVID bit descriptions
Bits Name Description
[31:16] - Reserved, RAZ
[15:0] NUM Identifies the device configuration:
9 No LPI available
11 LPI available but no ITS
14 LPI available and 1 × ITS
15 LPI available and 2 × ITS
16 LPI available and 3 × ITS
5.8.10 GICT_PIDR2, Peripheral ID2 Register
This register returns byte[2] of the peripheral ID. The GICT_PIDR2 register is part of the set of
trace and debug peripheral identification registers.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-45: GICT_PIDR2 bit assignments
ArchRevReserved
31 8 7 4 3
DES_1
02
JEDEC
Table 5-56: GICT_PIDR2 bit descriptions
Bits Name Description
[31:8] - Reserved, RAZ
[7:4] ArchRev Identifies the version of the GIC architecture with which the trace and debug block complies:
0x3 GICv3
[3] JEDEC Indicates that a JEDEC-assigned JEP106 identity code is used
[2:0] DES_1 Bits[6:4] of the JEP106 identity code. Bits[3:0] of the JEP106 identity code are assigned to
GICT_PIDR1[7:4].
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