Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Offset Name Type Reset Width Description Architecture
defined?
0xFFE8 GICM_PIDR2 RO 0x3B 32 Peripheral ID 2 register No
0xFFEC GICM_PIDR3 RO 0x00 32 Peripheral ID 3 register No
0xFFF0 GICM_CIDR0 RO 0x0D 32 Component ID 0 register No
0xFFF4 GICM_CIDR1 RO 0xF0 32 Component ID 1 register No
0xFFF8 GICM_CIDR2 RO 0x05 32 Component ID 2 register No
0xFFFC GICM_CIDR3 RO 0xB1 32 Component ID 3 register No
5.3.1 GICM_TYPER, Message-based Type Register
This register returns information about the number of SPIs that are assigned to the frame.
Configurations
This register is available in all configurations.
Attributes
Width 64-bit
Functional group See 5.3 Distributor registers (GICM) for message-based SPIs summary on
page 117 for the address offset, type, and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-17: GICM_TYPER bit assignments
31 30 29 28 16 15 11 10
0
NumSPISReservedINTID
Valid SR
CLR
63
32
Reserved
Table 5-20: GICM_TYPER bit descriptions
Bits Name Description
[63:32] - Reserved, RES0
[31] Valid Returns 1 to indicate that the register reports information about the capabilities of the frame
[30] CLR Returns 1 to indicate that the GICM_CLRSPI registers are present
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