ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
RTL parameter Function Range of options
REV_REG_TYPE Register slice type on B and R channels
0 None
1 Reverse
2 Forward
3 Full
3.5 SPI Collator
The SPI Collator converts SPI wires into messages to be sent to the Distributor.
The following figure shows the SPI Collator block.
Figure 3-6: SPI Collator
SPI Collator
Clock
Q-Channel
Power
Q-Channel
spi[m−1:0]
spi_r[m−1:0]
GICD
iccd*
AXI4-Stream
interfaces
icdc*
Individual SPIs can be synchronized into the SPI Collator, or the SPI Collator can be placed in
the same clock domain as the interrupt sources and the messages that are synchronized into the
Distributor.
Placing the SPI Collator in a clock domain that is always on and is remote from the GIC Distributor
enables more aggressive power saving because the Distributor can be clock gated hierarchically.
3.5.1 SPI Collator AXI4-Stream interface
The AXI4-Stream interface enables communication between the SPI Collator and the Distributor.
The AXI4-Stream ports apply only transient backpressure to the AXI4-Stream interface, which
enables packets to be routed over any free-flowing interconnect.
3.5.2 SPI Collator wires
The SPI Collator wires can be extended to create other functions.
By default, the asserted level of an SPI is active-HIGH, as with previous Arm GIC implementations.
However, each SPI can be either inverted, synchronized, or both, using the parameters SPI_INV[n]
and SPI_SYNC[n], where:
•
SPI_INV[n] == 1 indicates that the inverter is enabled
•
SPI_SYNC[n] == 1 indicates that the synchronizer is enabled
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