Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.10.9 FMU_SMINJERR, Safety Mechanism Inject Error register
This register injects one error into the specified Safety Mechanism inside a GIC block.
This feature cannot be used for the following FMU_SMINJERR field values:
•
BLK = GICD, SMID = 0
•
BLK = 3
•
BLK = PPI, SMID = 0
•
BLK = ITS, SMID = 0
•
BLK = SPI Collator, SMID = 0
•
BLK = Wake Request, SMID = 0
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.10 FMU register summary on page 179 for the address offset, type,
and reset value of this register.
Usage constraints
•
Only accessible by Secure accesses.
•
After a write to this register, poll FMU_STATUS.idle to ensure that the effect of the write is
complete.
•
Do not write to FMU_SMINJERR and inject an error that corresponds to a powered-off block.
See Power management on page 208.
Bit descriptions
Figure 5-69: FMU_SMINJERR bit assignments
Table 5-83: FMU_SMINJERR bit descriptions
Bits Name Description
[31:24] SMID Safety Mechanism identifier.
See Table 6-2: Safety Mechanism IDs on page 199 for Safety Mechanism ID encodings.
[23:16] - Reserved, RAZ
[15:8] BLK Block identifier.
See Table 6-1: Error record block IDs on page 198 for block ID encodings.
[7:0] - Reserved, RAZ
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