Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-22: GICR_FCTLR bit assignments
31 30 7 6 4 3 1
0
Reserved
CGOReserved
SIPQD
Table 5-26: GICR_FCTLR bit descriptions
Bits Name Description
[31] QD Q-Channel deny:
0 Allow Q-Channel accesses
1 Deny Q-Channel accesses
[30:7] - Reserved, RAZ/WI
[6:4] CGO Clock gate override. One bit per clock gate:
0 Use full clock gating
1 Leave clock running. If clock gates are not implemented, then you must use this value.
The clock gate bit assignments are:
Bit[6], CGO[2] Search clock gate
Bit[5], CGO[1] Downstream message clock gate
Bit[4], CGO[0] Upstream message clock gate
[3:1] - Reserved, RAZ/WI
[0] SIP Scrub in progress:
0 No scrub in progress
1 Scrub in progress
This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0.
5.4.5 GICR_PWRR, Power Register
This register controls the powerup sequence of the Redistributors. Software must write to this
register during the powerup sequence.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.4 Redistributor registers for control and physical LPIs summary on page
121 for the address offset, type, and reset value of this register.
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