Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
3.5.5 SPI Collator configuration
You can configure several options that relate to the operation of the SPI Collator block.
Table 3-12: Configurable options for the SPI Collator
Feature Range of options
The number of SPI wires 0-960, in multiples of
32
SPI_INV is a wide vector of one bit for each SPI, indicating whether to invert the interrupt True, False
SPI_SYNC is a wide vector of one bit for each SPI, indicating whether to synchronize the
interrupt
True, False
For more information, see the Arm
®
CoreLink
™
GIC-600AE Generic Interrupt Controller Configuration
and Integration Manual.
3.6 Wake Request
The Wake Request block converts AXI4-Stream wake requests into one wake_request signal for
each core. Each wake_request signal connects to the system power controller.
The following figure shows the Wake Request block.
Figure 3-7: Wake Request
Wake Request
Distributor
wake_request
wake_request
wake_request
wake_request
wake_request
icdw*
AXI4-Stream
interface
A wake_request signal wakes a powered-down core when one of the following conditions is true:
•
An interrupt that targets only that specific core is pending
•
GICD_CTLR.E1NWF is set, and a 1-of-N SPI has selected that core as its target.
The GIC-600AE does not know whether a core is powered up or down. It only knows
whether software has enabled sending transactions on the AXI4-Stream interface. Therefore,
a wake_request signal remains asserted after a core has powered up. A wake_request signal
deasserts when software clears GICR_WAKER.ProcessorSleep and the GIC-600AE clears the
GICR_WAKER.ChildrenAsleep bit.
If there are pending interrupts, either targeted or 1-of-N when GICR_WAKER.ProcessorSleep is set,
the wake_request signal might assert during the powerdown sequence. The power controller must
ignore the wake_request signal until the core is powered down.
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