EasyManuals Logo

ARM CoreLink GIC-600AE User Manual

Default Icon
268 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #100 background imageLoading...
Page #100 background image
Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Offset Name Type Reset Width Description Architecture
defined?
0x0E00-
0x0EFC
GICD_NSACRn
3
RW 0x0 32 Non-secure Access Control Registers, n = 0-63, but
n=0-1 are Reserved when affinity routing is enabled
Yes
0x0F00-
0x5FFC
- - - - Reserved -
0x6000-
0x7FF8
GICD_IROUTERn RW 0x0080000000 64 Interrupt Routing Registers, n = 0-991, but n=0-31 are
Reserved when affinity routing is enabled.
See the GICv3 and GICv4 Software Overview.
All SPIs are reset with Interrupt_Routing_Mode == 1.
The first register is GICD_IROUTER32.
Yes
0xC000 GICD_CHIPSR RO P-Channel
dependent
32 Chip Status Register. Reserved in single-chip
configurations.
No
0xC004 GICD_DCHIPR RW 0x0 32 Default Chip Register. Reserved in single-chip
configurations.
No
0xC008-
0xC080
GICD_CHIPRn RW 0x0 64 Chip Registers, n = 0-15. Reserved in single-chip
configurations.
No
0xC088-
0xDFFC
- - - - Reserved -
0xE000-
0xE0FC
GICD_ICLARn RW 0x0 32 Interrupt Class Registers, n = 0-63, but n=0-1 are
Reserved
No
0xE100-
0xE17C
GICD_ICERRRn RW 0x0 32 Interrupt Clear Error Registers, n = 0-31, but n=0 is
Reserved
No
0xE180-
0xEFFC
- - - - Reserved -
0xF000 GICD_CFGID RO Configuration
dependent
64 Configuration ID Register No
0xF008-
0xFFCC
- - - - Reserved -
0xFFD0 GICD_PIDR4 RO 0x44 32 Peripheral ID 4 Register No
0xFFD4 GICD_PIDR5 RO 0x00 32 Peripheral ID 5 Register No
0xFFD8 GICD_PIDR6 RO 0x00 32 Peripheral ID 6 Register No
0xFFDC GICD_PIDR7 RO 0x00 32 Peripheral ID 7 Register No
0xFFE0 GICD_PIDR0 RO 0x92 32 Peripheral ID 0 Register No
0xFFE4 GICD_PIDR1 RO 0xB4 32 Peripheral ID 1 Register No
0xFFE8 GICD_PIDR2 RO 0x3B 32 Peripheral ID 2 Register No
0xFFEC GICD_PIDR3 RO 0x00 32 Peripheral ID 3 Register No
0xFFF0 GICD_CIDR0 RO 0x0D 32 Component ID 0 Register No
0xFFF4 GICD_CIDR1 RO 0xF0 32 Component ID 1 Register No
0xFFF8 GICD_CIDR2 RO 0x05 32 Component ID 2 Register No
0xFFFC GICD_CIDR3 RO 0xB1 32 Component ID 3 Register No
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 100 of 268

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ARM CoreLink GIC-600AE and is the answer not in the manual?

ARM CoreLink GIC-600AE Specifications

General IconGeneral
BrandARM
ModelCoreLink GIC-600AE
CategoryController
LanguageEnglish

Related product manuals