Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bit descriptions
Figure 5-42: GICT_ERRGSR bit assignments
31
0
Status
63
32
Status
Table 5-53: GICT_ERRGSR bit descriptions
Bits Name Description
[n] Status Indicates the status of error record n, where n is 0-13+ depending on the configuration:
0 The error record is not reporting any errors
1 The error record is reporting one or more errors
5.8.8 GICT_ERRIRQCR<n>, Error Interrupt Configuration Registers
GICT_ERRIRQCR0 controls which SPI is generated when a fault handling interrupt occurs.
GICT_ERRIRQCR1 controls which SPI is generated when an error recovery interrupt occurs.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.8 GICT register summary on page 147 for the address offset, type,
and reset value of this register.
Usage constraints
If GICD_SAC.GICTNS == 0, then only Secure software can access the functions of this register.
Bit descriptions
Figure 5-43: GICT_ERRIRQCR<n> bit assignments
31 10 9
0
SPIIDReserved
Table 5-54: GICT_ERRIRQCR<n> bit descriptions
Bits Name Description
[31:10] - Reserved, RAZ
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 160 of 268
To Next Page
Loading...