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Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
The GIC-600AE uses two methods to support this:
The MSI-64 Encapsulator modifies the page address of accesses to the architectural
GITS_TRANSLATER address, set by the msi_translator_page tie-off signal, to the system-
defined page set by the msi64_translator_page signal.
When the ITS shares an ACE-Lite subordinate port, the its_transr_page_offset tie-off
signal allows the GITS_TRANSLATER register page to be moved to anywhere in the
address map, to match the msi64_translator_page signal value that is independent of the
GICD address map reset.
The msi64_translator_page and its_transr_page_offset signals, or one of either, must not
be on top of any other GIC register page.
To ensure that this method of mapping is hidden from software, all accesses to the
GITS_TRANSLATER register must pass through an Encapsulator, or similar embedded
functionality. See 3.4 MSI-64 Encapsulator on page 40 for more information.
The following figure shows an example of how to integrate the MSI-64 Encapsulator in
a system. The MSI-64 Encapsulator connects upstream of the interconnect and targets
an ITS downstream of the interconnect. In this scenario, the DeviceID is transported on
the data channels of the interconnect to the ITS. This topology benefits those systems
where the width of the awuser signal on the interconnect is too narrow to transport the
DeviceID.
Figure 4-3: MSI-64 Encapsulator with DeviceID sent in the data[63:32] bits
Device
MSI-64 Encapsulator
Interconnect
ITS
4.13 RAMs and ECC
The GIC-600AE uses multiple RAMs to store a range of states for all types of interrupt. In typical
operation, the RAMs are transparent to software.
Each RAM is protected from errors using an ECC with Single Error Correction and Double Error
Detection (SECDED).
If single or double errors are detected, they are reported in the software visible error records, see
4.15 Reliability, Accessibility, and Serviceability on page 68 for more information.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
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