Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
3.3 Interrupt Translation Service
The ITS provides a software mechanism for translating message-based interrupts into LPIs. The ITS
is supported optionally in configurations that support LPIs.
A peripheral generates an LPI by writing to the GITS_TRANSLATER in the ITS. The write provides
the ITS with the following information:
•
EventID (VID). A value that is written to GITS_TRANSLATER. The EventID identifies which
interrupt the peripheral is sending. Each interrupt source is identified by an Interrupt Identifier
(INTID). The EventID might be the same as the INTID, or it might be translated by the ITS into
the INTID.
•
DeviceID (DID). The DeviceID is a unique identifier that identifies the peripheral.
The following figure shows the ITS block.
Figure 3-3: ITS block
ITS base address,
target_address
ITS
Q-Channel
its_id[7:0]
its_transr_page_offset
icid*
GICD
icdi*
AXI4-Stream
interfaces
The ITS is an implementation of the GICv3 Interrupt Translation Service as described in the Arm
®
Generic Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
The ITS translates MSI requests to the required LPI and target. It also has a set of commands for
managing LPIs for core power management and load balancing.
A main use of the ITS is the translation of MSI/MSIx messages from a PCIe Root Complex (RC).
To complete the translation, the ITS must be supplied with a DeviceID that is derived from the
PCIe RequestorID. To reduce the distance that the DeviceID is transferred and to enable better
compartmentalization between RCs, the ITS is best placed next to the RC. To ease integration, the
ITS has an optional bypass switch as shown in the ITS block diagram. If the bypass switch is not
configured, the ACE-Lite subordinate and manager ports connect to the ITS directly. See 3.3.1 ITS
ACE-Lite subordinate interface on page 36 and 3.3.2 ITS ACE-Lite manager interface on page
37.
In accordance with PCIe dependency rules, read responses on a PCIe Root Complex subordinate
port must be ordered against completion of posted writes on a Root Complex manager port.
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