Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
5.2.9 GICD_ICLARn, Interrupt Class Registers
These registers control whether a 1 of N SPI can target a core that is assigned to class 0 or class
1 group. Each register controls 16 SPIs and the GIC-600AE has 60 registers, GICD_ICLAR2-
GICD_ICLAR61.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.2 Distributor registers (GICD/GICDA) summary on page 98 for the
address offset, type, and reset value of this register.
Usage constraints
The Distributor provides up to 60 registers to support 960 SPIs. If you configure the GIC-600AE to
use fewer than 960 SPIs, then it reduces the number of registers accordingly. For locations where
interrupts are not implemented, the register is RAZ/WI.
These registers are only accessible when the corresponding
GICD_IROUTERn.Interrupt_Routing_Mode == 1.
Bit descriptions
Figure 5-9: GICD_ICLARn bit assignments
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
nn+1n+2n+3n+4n+5n+6n+7n+8n+9n+10n+11n+12n+13n+14n+15
Class
0
Table 5-11: GICD_ICLARn bit descriptions
Bits Name Description
[31:0]
Bits[2x+1:2x], for
x = 0 to 15
Class<x> Controls whether the 1 of N SPI can target a core, depending on the class group that the
core is assigned to:
0b00 The SPI can target a core that is assigned to class 0 or class 1
0b01 The SPI can target a core that is assigned to class 1
0b10 The SPI can target a core that is assigned to class 0
0b11 The SPI cannot target a core that is assigned to class 0 or class 1
The SPI that a bit refers to, depends on its bit position and the base address offset of the
GICD_ICLARn, that is, SPI = 16×n + bit[number]/2.
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