Arm
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CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Programmers model
Bits Name Description
[4:0] OVS Overflow status. The OVS[n] bit is the overflow clear for counter n. This field resets to zero. Reads
return the state of the overflow status bits.
Writing:
Bit[n] = 1 Clears the overflow status for counter n
Bit[n] = 0 No effect. To set a counter overflow status, use GICP_OVSSET0.
Overflow of counter n, that is a transition past the maximum unsigned value of the counter that causes
the value to wrap and become zero, sets the corresponding OVS bit. In addition, this event can trigger
the PMU interrupt and cause a capture of the PMU counter values, see 5.9.2 GICP_EVTYPERn, Event
Type Configuration Registers on page 164.
5.9.10 GICP_OVSSET0, Overflow Status Set Register 0
This register provides the set mechanism for the counter overflow status bits and provides read
access to the counter overflow status bit values. The GIC-600AE supports five counters, n = 0-4.
Configurations
This register is available in all configurations.
Attributes
Width 32-bit
Functional group See 5.9 GICP register summary on page 163 for the address offset, type,
and reset value of this register.
Usage constraints
There are no usage constraints.
Bit descriptions
Figure 5-55: GICP_OVSSET0 bit assignments
31 5 4
0
OVSReserved
Table 5-68: GICP_OVSSET0 bit descriptions
Bits Name Description
[31:5] - Reserved, RAZ
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