ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Signal descriptions
P-Channel device interface for chip-level save and restore
Signal Direction Description
preq Input
pstate[4:0] Input
paccept Output
pdeny Output
pactive Output
This P-Channel device interface is only present in multichip configurations.
See 4.16.4 Power control and P-Channel on page 91.
The preq signal is synchronized into the GIC-600AE.
The pstate signal must be stable when the preq signal is asserted.
This bus must be treated asynchronously.
A.3 Interrupt signals
The GIC-600AE has interrupt signals for SPIs and PPIs.
Signal definitions
Table A-3: Interrupt signals
Signal Direction Description
ppi<n>[_<ppi_block>][_<bus>]
[<cpus>−1:0]
If there are:
•
8 PPIs per core, n is 22-27, 29,
or 30.
•
12 PPIs per core, n is 20-31.
•
16 PPIs per core, n is 16-31.
Input PPI input wires for interrupt <n>. One bit per core.
The PPIs for each core are independent and are typically used for peripherals that are
not shared between cores. For example, timers on the core typically use PPIs.
By default, PPIs are active-LOW. The GIC provides top-level RTL parameters so that a
PPI can be active-HIGH.
The GIC also provides top-level RTL parameters so that a PPI can be synchronized to
the clk signal.
By default, PPIs are level-sensitive interrupts. However, software can change an
interrupt to be edge triggered by programming the GICR_ICFGR1 register.
ppi<n>_r_[_<ppi_block>][_<bus>] Output PPI output after synchronization and edge detection. You can use these signals to create
pulse extenders for edge-triggered interrupts that cross clock domains.
spi[spi_wire−1:0]
The spi_wire configuration
parameter controls the number of
SPIs.
Input This signal is the number of SPI wires that the GIC supports.
Note:
This is not the same as the number of SPIs supported because they could be message-
based only or be on another chip.
By default, SPIs are active-HIGH. The GIC provides top-level RTL parameters so that an
SPI can be active-LOW.
The GIC also provides top-level RTL parameters so that an SPI can be synchronized to
the clk signal.
spi_r[spi_wire−1:0]
The spi_wire configuration
parameter controls the number of
SPIs.
Output SPI output after synchronization and edge detection. Can be used for cross-domain
pulse detection.
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