ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Signal descriptions
A.4 CPU interface signals
The CPU interface signals of a cluster connect to a Redistributor using two GIC Stream interfaces.
In the following tables, <ppi_num>, <bus>, and <cpus> are configuration options that are set
using the ppi_ref, bus, and cpus parameters. See the Arm
®
CoreLink
™
GIC-600AE Generic Interrupt
Controller Configuration and Integration Manual for more information.
Signal definitions
Table A-4: CPU interface signals
GIC Stream-compliant bus for communication from a cluster to a Redistributor
Signal Direction Description
icctready[_<ppi_num>]
[_<bus>]
Output
icctvalid[_<ppi_num>]
[_<bus>]
Input
icctdata[_<ppi_num>]
[_<bus>][15:0]
Input
icctid[_<ppi_num>]
[_<bus>][<cpus>−1:0]
Input
icctlast[_<ppi_num>]
[_<bus>]
Input
This GIC Stream-compliant bus is fully credited and can be sent over any free-flowing interconnect.
For more information, see Table A-2 CPU interface to upstream Redistributor interface in the GIC Stream
Protocol interface Appendix of the Arm
®
Generic Interrupt Controller Architecture Specification, GIC
architecture version 3 and version 4.
If the cluster issues IDs on the ICCTID signal with values other than <cpus−1:0>, then the behavior
is unpredictable.
icctwakeup[_<ppi_num>]
[_<bus>]
Input Registered wake signal to indicate that a message is arriving or is about to arrive on the icc bus
GIC Stream-compliant bus for communication from a Redistributor to a cluster
Signal Direction Description
iritready[_<ppi_num>]
[_<bus>]
Input
iritvalid[_<ppi_num>]
[_<bus>]
Output
iritdata[_<ppi_num>]
[_<bus>][15:0]
Output
iritdest [_<ppi_num>]
[_<bus>][<cpus>−1:0]
Output
iritlast[_<ppi_num>]
[_<bus>]
Output
This GIC Stream-compliant bus is fully credited and can be sent over any free-flowing interconnect.
For more information, see Table A-1 Redistributor to downstream CPU interface in the GIC Stream
Protocol interface Appendix of the Arm
®
Generic Interrupt Controller Architecture Specification, GIC
architecture version 3 and version 4.
iritwakeup[_<ppi_num>]
[_<bus>]
Output Registered wake signal to indicate that a message is arriving or is about to arrive on the IRI bus of the
cluster
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