Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Operation
Level-sensitive
The interrupt is pending while the interrupt input is asserted. As with previous Arm GICs,
PPIs are active-LOW, whereas SPIs are active-HIGH by default. However, you can change
these default settings, see 4.1 Interrupt types on page 48 for more information.
Edge-triggered
A rising-edge on the interrupt input causes the interrupt to become pending. The pending bit
is cleared later when the interrupt is activated by the CPU interface.
To set the correct settings for the system, you must program the GICD_ICFGRn and GICR_ICFGR1
registers.
The GIC-600AE provides optional synchronizers on every interrupt wire input and also return
signals, to enable pulse extenders when sending edge-triggered interrupts across domain
boundaries, see 3.5.2 SPI Collator wires on page 42.
For more information, see the GICv3 and GICv4 Software Overview and the Arm
®
Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
4.4 Affinity routing and assignment
The GIC-600AE uses affinity routing, a hierarchical scheme, to identify connected cores and for
routing interrupts to specific cores.
The Arm architecture defines a register in a core that identifies the logical address of the core in
the system. This register, which is known as the Multiprocessor Identification Register (MPIDR), has a
hierarchical format. Each level of the hierarchy is known as an affinity level, with the highest affinity
level specified first:
•
For 32-bit Armv8 processors, the MPIDR defines three levels of affinity, with an implicit affinity
level 3 value of 0.
•
For 64-bit Armv8 processors, the MPIDR defines four levels of affinity.
The GIC-600AE regards each hardware thread of a processor that supports multiple hardware
threads as a single independent core.
The affinity of a core is represented by four 8-bit fields using dot-decimal notation,
<Aff3>.<Aff2>.<Aff1>.<Aff0>, where Affn is a value for affinity level n. An example of an
identification for a specific core would be 0.255.0.15.
The affinity scheme matches the format of the MPIDR_EL1 register in Armv8-A. System designers
must ensure that the ID reported by the core of the MPIDR_EL1 register matches how the core
connects to the interrupt controller.
The GIC-600AE allows fully flexible allocation of MPIDR. However, it has two built-in default
assignments that are based on the aff0_thread configuration parameter:
aff0_
thread == 1
The four fields map to 0.<cluster>.<core>.<thread>
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