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ARM CoreLink GIC-600AE User Manual

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Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Components and configuration
The qreqn input signal is synchronized inside the Redistributor. The qactive signal is connected to
the PPI wires directly, and must be considered as an asynchronous output.
Related information
Power control signals on page 251
3.2.4 Redistributor PPI signals
GIC-600AE supports 8, 12, or 16 PPIs, and synchronized output return wires, for each core. The
number of PPIs and return wires must be the same for all cores sharing a Redistributor.
Level-sensitive PPI signals are active-LOW by default, as with previous Arm GIC implementations.
However, individual PPI signals can be inverted and synchronized using the following build-time
parameters:
GIC600AE_<usrcfg>_PPI<ppi_id>_<cpu_number>_<ppi_number>_<INV>
GIC600AE_<usrcfg>_PPI<ppi_id>_<cpu_number>_<ppi_number>_<SYNC>
Where <usrcfg> is user-defined text that is assigned when the GIC is configured, which can
help with identifying a GIC configuration.
Every ppi<n> signal has a corresponding ppi<n>_r signal, from after the synchronizer or capture
flop. These ppi<n>_r signals can be used to create pulse extenders for edge-triggered interrupts
that cross clock domains.
If you plan to use edge-triggered PPIs and use the Q-Channel to clock gate the Redistributor
hierarchically, then you must include pulse extenders. The pulse extenders ensure that interrupts
are not missed while the clock restarts.
For information about the purpose of each PPI used by the core in your system, refer to the
relevant core Technical Reference Manual.
3.2.5 Redistributor configuration
You can configure several options that relate to the operation of the Redistributor block.
Table 3-7: Configurable options for the Redistributor
Feature Range of options
Number of cores downstream 1-64
PPIs per core 8, 12, 16
ECC support. See 4.15 Reliability, Accessibility, and Serviceability on page 68 for more
information.
True, False
Bus data width 16, 32
GIC Stream bus structure Flexible buses and
domains
For more information, see the Arm
®
CoreLink
GIC-600AE Generic Interrupt Controller Configuration
and Integration Manual.
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
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ARM CoreLink GIC-600AE Specifications

General IconGeneral
BrandARM
ModelCoreLink GIC-600AE
CategoryController
LanguageEnglish

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